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ds07-12536-2e fujitsu semiconductor data sheet 8-bit proprietary microcontroller cmos f 2 mc-8l mb89940 series mb89943/p945/pv940 n outline the mb89940 series is specially designed for automotive instrumentation applications. it features a combination of two pwm pulse generators and four high-drive-current outputs for controlling a stepping motor. it also contains two analog inputs, two pwm pulse generators and 10-digit lcd controller/driver for various sensor/indicator devices. the mb89940 series is manufactured with high performance cmos technologies and packaged in a 48-pin qfp. n features ? 8-bit core cpu; 4 mhz system clock (8 mhz external, 500 ns instruction cycle) ? 21-bit watchdog timer ? clock generator/controller ? 16-bit interval timer ? two pwm pulse generators with four high-drive-current outputs ? two-channel 8-bit a/d converter ? three external interrupt ? low supply voltage reset ? external voltage monitor interrupt ? two more pwm pulse generators for controlling indicator devices ? 4-common 17-segment lcd driver/controller ? package; 48-pin plastic qfp, 48-pin ceramic mqfp (continued) n pac k ag e 48-pin plastic qfp (fpt-48p-m16) 48-pin ceramic mqfp (mqp-48c-p01)
2 mb89940 series (continued) ? 5.0 v single power supply (v pp required for MB89P945) ?0.8 m m cmos technology (mb89pv940 and MB89P945) ?0.5 m m cmos technology (mb89943) ? on-chip voltage regulator for internal 3.0 v power supply (mb89943) n product lineup (continued) MB89P945 mb89pv940 classification mass-produced products (mask rom products) one-time prom piggyback rom size 8 k 8 bits (internal mask rom) 16 k 8 bits (internal prom) 32 k 8 bits (external on piggyback) ram size 512 8 bits 1 k 8 bits cpu functions the number of instructions: 136 instruction cycle: 0.5 m s* 1 @8 mhz interrupt response time: 4.0 m s* 1 @8 mhz multiply instruction time: 19 instruction cycles divide instruction time: 21 instruction cycles direct addressing memory-to/from-register data transfer: 7 instruction cycles ports output: 5-bit n-ch open-drain input/output: two 8-bit cmos schmitt i/os and 8-bit cmos i/os timebase timer 21 bits interrupt interval: 1 ms, 4.1 ms, 32.8 ms or 524.3 ms 8-bit/16-bit timer can be used as two 8-bit timers or one 16-bit timer operation clock: 1 m s, 16 m s, 256 m s or external * 1 watchdog reset reset interval: approx. 524 ms to 1049 ms stepping motor controller two 8-bit pwm pulse generators synchronized 4-channel high current output operation clock: 250 ns, 500 ns, 1 m s or 4 m s* 1 8-bit pwm timers two 8-bit pwm timers external interrupt 3 channels, selective positive edge or negative edge trigger a/d converter 8-bit resolution, two-channel input conversion time: 44 instruction cycles for a/d conversion, 12 instruction cycles for sense mode operation lcd controller 4-common and 17-segment outputs number of outputs programmable low supply voltage reset autonomous reset when low supply voltage reset voltage: 3.3 v, 3.6 v, 4.0 v external voltage monitor interrupt interrupts when voltage at external pin is lower than the reference voltage standby modes stop mode and sleep mode operating voltage* 2 3.5 v to 5.5 v mb89943 part number item
3 mb89940 series (continued) *1: execution times and clock cycle times are dependent on the use of mcu. *2: varies with conditions such as the operating frequency. (see section n electrical characteristics.) in the case of the mb89pv940, the voltage varies with the vestrictions of the eprom for use. n package and corresponding products : available : not available note: for more information about each package, see section n package dimensions. MB89P945 mb89pv940 process cmos external eprom mbm27c256a-20tvm package mb89943 MB89P945 mb89pv940 fpt-48p-m16 mqp-48c-p01 mb89943 part number item
4 mb89940 series n differences among products 1. memory size prior to evaluating/developing the software for the mb89940 series, please check the differences between the product types. ? ram/rom configurations are dependent on the product type. ? if the bottom address of the stack is set to the upper limit of the ram address, it should be relocated when changing the product type. 2. power dissipation ? for the piggyback product, add the power dissipation of the eeprom on the piggyback. ? the power dissipation differs between the product types. 3. technology the mask rom product is fabricated with a 0.5 m m cmos technology whereas the other products with 0.8 m m cmos technology. also the mask rom product contains the on-chip voltage regulator for the internal 3.0 power supply. for details, refer to mb89940 series hardware manual . 4. mask option functions that can be selected as options and how to designate these options vary by the product. before using options check section n mask options. ? no options are available for the piggyback product. ? the power-on reset and reset output options are always activated with the mask rom product. ? pull-up option must not be specified with the pins used as lcd outputs.
5 mb89940 series n pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 av cc rst p41/com0 p42/com1 x0 x1 v cc p43/com2 p44/com3 p27/int2 p26/int1 p25/int0 36 35 34 33 32 31 30 29 28 27 26 25 dv cc p30/fuelo p00/seg00 p01/seg01 p02/seg02 p03/seg03 p04/seg04 p05/seg05 p06/seg06 p07/seg07 p10/seg08 p11/seg09 48 47 46 45 44 43 42 41 40 39 38 37 mode vint p40/pw p37/fueli p36/tempi av ss dv ss p35/pwm2m p34/pwm2p p33/pwm1m p32/pwm1p p31/tempo 13 14 15 16 17 18 19 20 21 22 23 24 p24/v3 p23/to/v2 p22/ec/v1 p21/v0 p20/seg16 p17/seg15 v ss p16/seg14 p15/seg13 p14/seg12 p13/seg11 p12/seg10 (top view) (fpt-48p-m16)
6 mb89940 series ? pin assignment on package top (mb89pv940 only) n.c.: internally connected. do not use. pin no. pin name pin no. pin name pin no. pin name pin no. pin name 49a1557n.c.65o473oe 50a1258a266o574n.c. 51 a7 59 a1 67 o6 75 a11 52 a6 60 a0 68 o7 76 a9 53 a5 61 o1 69 o8 77 a8 54 a4 62 o2 70 ce 78 a13 55 a3 63 o3 71 a10 79 a14 56 n.c. 64 v ss 72 n.c. 80 v cc 1 2 3 4 5 6 7 8 9 10 11 12 av cc rst p41/com0 p42/com1 x0 x1 v cc p43/com2 p44/com3 p27/int2 p26/int1 p25/int0 36 35 34 33 32 31 30 29 28 27 26 25 dv cc p30/fuelo p00/seg00 p01/seg01 p02/seg02 p03/seg03 p04/seg04 p05/seg05 p06/seg06 p07/seg07 p10/seg08 p11/seg09 48 47 46 45 44 43 42 41 40 39 38 37 mode vint p40/pw p37/fueli p36/tempi av ss dv ss p35/pwm2m p34/pwm2p p33/pwm1m p32/pwm1p p31/tempo 13 14 15 16 17 18 19 20 21 22 23 24 p24/v3 p23/to/v2 p22/ec/v1 p21/v0 p20/seg16 p17/seg15 v ss p16/seg14 p15/seg13 p14/seg12 p13/seg11 p12/seg10 (top view) (mqp-48c-p01) 77 78 79 80 49 50 51 52 68 67 66 65 64 63 62 61 69 70 71 72 73 74 75 76 60 59 58 57 56 55 54 53
7 mb89940 series n pin description (continued) *1: fpt-48p-m16 *2: mqp-48c-p01 pin no. pin name circuit type function qfp* 1 mqfp* 2 5 5 x0 a these pins are used for crystal oscillation. x0 and x1 can be directly connected to a crystal oscillator. when the oscillation clock is provided to x0 externally, x1 should be left open. 66x1 48 48 mode b the mode input is used for entering the mpu into the test mode. in user applications, mode is connected to v ss . 22rst c applying a reset pulse to this pin forces the mpu to enter the initial state. rst is active low and drives low state when an internal reset occurs. reset pulses of the duration less than the minimum pulse width may cause the mcu to enter undefined states. 34 to 27 34 to 27 p00/seg00 to p07/seg07 h these pins have two functions. their functions can be switched between port 0 and lcd segment signal outputs by setting the internal registers of the lcd controller. 26 to 20, 18 26 to 20, 18 p10/seg08 to p17/seg15 j these pins have two functions. their functions can be switched between port 1 and lcd segment signal outputs by setting the internal registers of the lcd controller. 17 17 p20/seg15 i this pin can be used as the bit 0 of port 2 or an lcd segment signal output by setting the internal register of the lcd controller. 16 16 p21/v0 f this pin is the bit 1 of port 2. this pin can also be used for an external lcd bias voltage input. 15 15 p22/ec/v1 f this pin can be used as the bit 2 of port 2 or the external clock input for the interval timer. this pin can also be used for an external lcd bias voltage input. 14 14 p23/to/v2 f this pin can be used as the bit 3 of port 2 or the output for the interval timer. its function can be switched by setting the internal register of the interval timer. this pin can also be used for an external lcd bias voltage input. 13 13 p24/v3 f this pin can be used as the bit 4 of port 2 or an external lcd bias voltage input. 12, 11, 10 12, 11, 10 p25/int0 to p27/int2 e these pins are used for port 2. they can also be used for external interrupt inputs. 35 35 p30/fuelo d this pin can be used for the bit 0 of port 3 or the output from pwm3. the function of this pin can be switched by setting the internal register of pwm3.
8 mb89940 series (continued) *1: fpt-48p-m16 *2: mqp-48c-p01 pin no. pin name circuit type function qfp* 1 mqfp* 2 37 37 p31/tempo g this pin can be used for the bit 1 of port 3 or the output from pwm4. the function of this pin can be switched by setting the internal register of pwm4. this output has a high drive-current capability. 38, 39 38, 39 p32/pwm1p, p33/pwm1m g these pins are the pair of high-current driver outputs for one of two motor coils. they can be also used for the bits 2 and 3 of port 3 by setting the internal register of the stepper motor controller. 40, 41 40, 41 p34/pwm2p, p35/pwm2m g these pins are the pair of high-current driver outputs for one of two motor coils. they can be also used for the bits 4 and 5 of port 3 by setting the internal register of the stepper motor controller. 44 44 p36/tempi m this analog input is connected to channel 1 of the a/d converter. it can also be used for the bit 6 of port 3 when this a/ d input enable register bit is set to 0. 45 45 p37/fueli m this analog input is connected to channel 0 of the a/d converter. it can also be used for the bit 7 of port 3 when this a/ d input enable register bit is set to 0. 46 46 p40/pw l this pin has two functions. when this pin is used as an open-drain output of port 4, the external voltage monitor reset should be in the power down mode. when it is used as the pw input of external voltage monitor reset, the corresponding bit of the port data register should be set to 1. 3, 4 8, 9 3, 4 8, 9 p41/com0 to p44/com3 k these pins are the lcd common signal outputs. when lcd is not used, these pins can be also used for port 4. 47 47 vint an external capacitor should be connected to this pin for stabilizing the internal 3.0 v power supply. for mb89pv940 and MB89P945, this pin should be left open. 77v cc v cc 19 19 v ss v ss 11av cc the power supply pin for the analog circuit the same voltage should be applied as v cc . 43 43 av ss the power supply pin for the analog circuit the same voltage should be applied as v ss . 36 36 dv cc the dedicated power supply pin for the high-current driver output the same voltage should be applied as v cc . 42 42 dv ss the dedicated power supply pin for the high-current driver output the same voltage should be applied as v ss .
9 mb89940 series ? external eprom pins (mb89pv940 only) pin no. pin name i/o function 49 50 51 52 53 54 55 58 59 60 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 o address output pins 61 62 63 65 66 67 68 69 o1 o2 o3 o4 o5 o6 o7 o8 i data input pins 70 ce o rom chip enable pin outputs h during standby. 71 a10 o address output pin 73 oe o rom output enable pin outputs l at all times. 75 76 77 78 79 a11 a9 a8 a13 a14 o address output pin 80 v cc o eprom power supply pin 64 v ss o power supply (gnd) pin 56 57 72 74 n.c. internally connected pins be sure to leave them open.
10 mb89940 series n i/o circuit type (continued) type circuit remarks a ? oscillator i/o with feedback resistor of approx. 2 m w . b ? schmitt-trigger input (pull-down resistance only for mb89943) c ? open-drain output with pull-up resistor (approx. 50 k w ). ? schmitt-trigger input ? hysteresis input d?cmos i/o e ? cmos i/o (schmitt trigger) ? pull-up resistor optional x1 x0 standby control signal r p-ch r n-ch p-ch n-ch p-ch n-ch r mask option
11 mb89940 series (continued) type circuit remarks f ? cmos i/o (schmitt trigger) ? external bias input ? pull-up resistor optional g ? cmos i/o (high output current) h?cmos i/o ? lcd controller/driver output i?cmos i/o ? lcd controller/driver output ? pull-up resistor optional ? hysteresis input p-ch n-ch r p-ch n-ch mask option p-ch n-ch p-ch n-ch p-ch n-ch p-ch n-ch p-ch n-ch p-ch n-ch p-ch n-ch r
12 mb89940 series (continued) type circuit remarks j?cmos i/o ? lcd controller/driver output ? pull-up resistor optional (except p11/seg09, p10/seg08) k ? n-ch open-drain output ? lcd controller/driver output l ? n-ch open-drain output ? analog input m?cmos i/o ? analog input p-ch n-ch p-ch n-ch p-ch n-ch r mask option n-ch p-ch n-ch p-ch n-ch n-ch p-ch n-ch
13 mb89940 series n handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on 1. absolute maximum ratings in section n electrical characteristics is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. also, take care to prevent the analog power supply (av cc and avr) and analog input from exceeding the digital power supply (v cc ) when the analog system power supply is turned on and off. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistor. the vint pin of mb89pv940 and MB89P945 is the only exception. 3. treatment of power supply pins on microcontrollers with a/d and d/a converters connect to be av cc = davc = v cc and av ss = avr = v ss even if the a/d and d/a converters are not in use. 4. treatment of n.c. pins be sure to leave (internally connected) n.c. pins open. 5. power supply voltage fluctuations although v cc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc ripple fluctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency (50 to 60 hz) and the transient fluctuation rate will be less than 0.1 v/ms at the time of a momentary fluctuation such as when power is switched.
14 mb89940 series n programming to the eprom on the MB89P945 1. programming MB89P945 using the eprom adapter (provided by fujitsu) and a standard eprom programmer, user-defined data can be written into the otprom and option prom. the eprom programmer should be set to mb27c256a-20tvm and electro-signature mode should not be used. when programming the data, the internal addresses are mapped as follows. 2. memory space 3. eprom programmer socket adapter please contact fujitsu for socket adapters for the MB89P945 and the eprom on the mb89pv940. 4. screening MB89P945 it is recommended that high-temperature aging is performed on the MB89P945 prior to the assembly. one time prom 16 kb one time prom 16 kb ffff h 0000 h 8000 h single chip address c000 h 7fff h 0000 h 3ff0 h 4000 h option prom eprom mode (corresponding addresses on the eprom programmer) program, verify aging +150?, 48 hrs. data verification assembly
15 mb89940 series 5. setting otprom options for MB89P945, mask options are described in the internal option prom area. the table below shows the bit map of the option prom. the option data can be written by a standard eprom programmer. ? otprom option bit map notes: default values are all 1. t osc : one oscillation clock cycle time when the bit 0 of 3ff3 h is 0, it activates the option setting for the low voltage reset control register. when this option is activated, software setting in the register has no effect. prom address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 3ff0 h unused unused unused reserved reset output 1: active 0: inactive power-on reset 1: active 0: inactive oscillation stabilization time 11: 2 18 t osc 10: 2 17 t osc 01: 2 14 t osc 3ff1 h p17 pull-up 1: inactive 0: active p16 pull-up 1: inactive 0: active p15 pull-up 1: inactive 0: active p14 pull-up 1: inactive 0: active p13 pull-up 1: inactive 0: active p12 pull-up 1: inactive 0: active unused unused 3ff2 h p27 pull-up 1: inactive 0: active p26 pull-up 1: inactive 0: active p25 pull-up 1: inactive 0: active p24 pull-up 1: inactive 0: active p23 pull-up 1: inactive 0: active p22 pull-up 1: inactive 0: active p21 pull-up 1: inactive 0: active p20 pull-up 1: inactive 0: active 3ff3 h unused unused unused low volt. pdx bit low volt. s1 bit low volt. s0 bit low volt. lve bit low volt. 1: register active 0: option active 3ff4 h unused unused unused unused unused unused unused unused 3ff5 h unused unused unused unused unused unused unused unused 3ff6 h unused unused unused unused unused unused unused unused
16 mb89940 series n programming to the eprom with piggyback/evaluation device 1. eprom for use mbm27c256a-20tvm 2. programming socket adapter please consult fujitsu. 3. memory space the memory space of the piggyback eprom is mapped onto the internal memory space as shown in the figure below. for eprom devices suitable for mb89pv940, please consult fujitsu. 4. programming to the eprom (1) set the eprom programmer to the mbm27c256a-20tvm. (2) load program data into the eprom programmer at 0000 h to 7fff h . (3) program to 0000 h to 7fff h with the eprom programmer. piggy back ffff h 0000 h 8000 h single chip address 7fff h 0000 h corresponding addresses on the eprom programmer eprom 32 kb
17 mb89940 series n block diagram x0 x1 p41/com0 to p44/com3 f 2 mc-8l core cpu interrupt controller oscillator external voltage monitor interrupt stepper motor macro port 3 8-bit a/d converter rst p40/pw p37/fueli p36/tempi dv cc dv ss p30/fuelo p31/tempo p32/pwm1p p33/pwm1m p34/pwm2p p35/pwm2m clock controller timebase timer reset circuit low supply voltage reset internal bus port 0, 1 and 4 port 2 ram rom pwm3 pwm4 pwm1 pwm2 interval timer lcd controller driver port 4 high-drive-current high-drive-current 4 v cc, v ss av cc , av ss vint other pins p10/seg08 to p17/seg15 8 p00/seg00 to p07/seg07 8 3 p20/seg16 p21/v0 p22/ec/v1 p23/to/v2 p24/v3 mode p25/int0 to p27/int2
18 mb89940 series n cpu core 1. memory space the mb89940 series has a memory space of 64 kbytes. all peripheral registers, ram and rom areas are mapped onto the 0000 h to ffff h range. the peripheral registers address below 007f h and the ram addresses the range 0080 h to 027f h (0080 h to 047f h for mb89pv940). a part of this ram area is also assigned as the general-purpose registers. the rom addresses above e000 h . the one-time prom addresses the range above c000 h . the external rom for the piggy sample addresses the range above 8000 h . the reset vector, interrupt vectors and vectors for vector-call instructions are stored in the highest addresses of the memory space. memory space rom 8 kb 512 b 16 kb 512 b 32 kb 1 kb ffff h 0000 h 0100 h 017f h 007f h mb89943 e000 h ram general- purpose registers peripheral registers one-time prom ffff h 0000 h 017f h 027f h 027f h 0100 h 007f h MB89P945 c000 h ram general- purpose registers peripheral registers external rom ffff h 0000 h 017f h 047f h 0100 h 007f h mb89pv940 8000 h ram general- purpose registers peripheral registers
19 mb89940 series 2. registers the f 2 mc-8l family has two types of registers; dedicated registers in the cpu and general-purpose registers in the memory. the following dedicated registers are provided: program counter (pc): a 16-bit register for indicating instruction storage positions accumulator (a): a 16-bit temporary register for storing arithmetic operations, etc. when the instruction is an 8-bit data processing instruction, the lower byte is used. temporary accumulator (t): a 16-bit register which performs arithmetic operations with the accumulator when the instruction is an 8-bit data processing instruction, the lower byte is used. index register (ix): a 16-bit register for index modification extra pointer (ep): a 16-bit pointer for indicating a memory address stack pointer (sp): a 16-bit register for indicating a stack area program status (ps): a 16-bit register for storing a register pointer, a condition code the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and the lower 8 bits for use as a condition code register (ccr). (see the diagram below.) pc a t ix ep sp ps 16 bits : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status fffd h indeterminate indeterminate indeterminate indeterminate indeterminate i-flag = 0, il1, 0 = 11 the other bit values are indeterminate. initial value structure of the program status register vacancy h i il1, 0 n z vc 54 rp ps 109876 3210 15 14 13 12 11 rp ccr vacancy vacancy
20 mb89940 series the rp indicates the address of the register bank currently in use. the relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. the ccr consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of cpu operations at the time of an interrupt. h-flag: set to 1 when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. cleared otherwise. this flag is for decimal adjustment instructions. i-flag: interrupt is enabled when this flag is set to 1. interrupt is disabled when the flag is cleared to 0. cleared to 0 at the reset. il1, 0: indicates the level of the interrupt currently allowed. processes an interrupt only if its request level is higher than the value indicated by this bit. n-flag: set to 1 if the msb becomes 1 as the result of an arithmetic operation. cleared to 0 otherwise. z-flag: set to 1 when an arithmetic operation results in 0. cleared to 0 otherwise. v-flag: set to 1 if the complement on 2 overflows as a result of an arithmetic operation. cleared to 0 if the overflow does not occur. c-flag: set to 1 when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared to 0 otherwise. set to 1 to the shift-out value in the case of a shift instruction. il1 il0 interrupt level high-low 00 1 high low 01 10 2 11 3 rule for conversion of actual addresses of the general-purpose register area ? a15 ? a14 ? a13 ? a12 ? a11 ? a10 ? a9 ? a8 r4 a7 r3 a6 r2 a5 r1 a4 r0 a3 b2 a2 b1 a1 b0 a0 rp generated addresses lower op codes
21 mb89940 series the following general-purpose registers are provided: general-purpose registers: an 8-bit register for storing data the general-purpose registers are 8 bits and located in the register banks of the memory. one bank contains eight registers and up to a total of 16 banks can be used on the mb89943 (ram 512 8 bits). the bank currently in use is indicated by the register bank pointer (rp). note: the number of register banks that can be used varies with the ram size. up to a total of 32 banks can be used on other than the mb89943. register bank configuration this address = 0100 h + 8 (rp) memory area 16 banks r 0 r 1 r 2 r 3 r 4 r 5 r 6 r 7
22 mb89940 series n i/o map (continued) address read/write register name register description 00 h (r/w) pdr0 port 0 data register 01 h (w) pdd0 port 0 data direction register 02 h (r/w) pdr1 port 1 data register 03 h (w) pdd1 port 1 data direction register 04 h to 06 h vacancy 07 h (r/w) scc system clock control register 08 h (r/w) smc standby mode control register 09 h (r/w) wdtc watchdog timer control register 0a h (r/w) tbtc timebase timer control register 0b h (r/w) lvrc low voltage reset control 0c h (r/w) pdr2 port 2 data register 0d h (w) pdd2 port 2 data direction register 0e h (r/w) pdr3 port 3 data register 0f h (w) pdd3 port 3 data direction register 10 h (r/w) pdr4 port 4 data register 11 h (r/w) ade port 3 a/d input enable register 12 h to 17 h vacancy 18 h (r/w) t2cr timer 2 control register 19 h (r/w) t1cr timer 1 control register 1a h (r/w) t2dr timer 2 data register 1b h (r/w) t1dr timer 1 data register 1c h to 1f h vacancy 20 h (r/w) adc1 a/d converter control register 1 21 h (r/w) adc2 a/d converter control register 2 22 h (r/w) adcd a/d converter data register 23 h (r/w) cntr pwm control register 24 h (w) comp1 pwm1 compare register 25 h vacancy 26 h (w) comp2 pwm2 compare register 27 h (r/w) selr1 pwm1 select register 28 h (r/w) selr2 pwm2 select register 29 h (r/w) cntr3 pwm3 control register 2a h (w) comp3 pwm3 compare register 2b h (r/w) cntr4 pwm4 control register
23 mb89940 series (continued) address read/write register name register description 2c h (w) comp4 pwm4 compare register 2d h (r/w) selt selector test register 2e h (r/w) pfc power fail control register 2f h (r/w) eir1 external interrupt control 1 register 30 h (r/w) eir2 external interrupt control 2 register 31 h to 5f h vacancy 60 h to 68 h (r/w) vram display data ram 69 h to 71 h vacancy 72 h (r/w) lcr1 lcd controller/driver register 73 h (r/w) lcr2 lcd controller/driver 2 register 74 h to 7b h vacancy 7c h (w) ilr1 interrupt level setting register 1 7d h (w) ilr2 interrupt level setting register 2 7e h (w) ilr3 interrupt level setting register 3 7f h vacancy
24 mb89940 series n electrical characteristics 1. absolute maximum ratings (v ss = 0.0 v) warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol value unit remarks min. max. power supply voltage v cc v ss C 0.3 v ss + 6.5 v av cc v ss C 0.3 v ss + 6.5 v should not exceed v cc dv cc v ss C 0.3 v ss + 6.5 v should not exceed v cc input voltage v i1 v ss C 0.3 v cc + 0.3 v except p31 to p35 and p41 to p44 v i2 v ss C 0.3 dv cc + 0.3 v p31 to p35 v i3 v ss C 0.3 v ss + 6.5 v p41 to p44 mb89pv940/945 v i4 v ss C 0.3 v cc + 0.3 v p41 to p44 mb89943 output voltage v o1 v ss C 0.3 v cc + 0.3 v except p31 to p35 and p41 to p44 v o2 v ss C 0.3 dv cc + 0.3 v p31 to p35 v o3 v ss C 0.3 v ss + 6.5 v p41 to p44 mb89pv940/945 v o4 v ss C 0.3 v cc + 0.3 v p41 to p44 mb89943 l level maximum output current v ol 20 ma except p31 to p35 50 ma p31 to p35 l level average output current v olav 4 ma except p31 to p35 40 ma p31 to p35 l level total maximum output current v oltotalmax 100 ma except p31 to p35 200 ma p31 to p35 l level total average output current v oltotalav 40 ma except p31 to p35 100 ma p31 to p35 h level maximum output current v oh C20 ma except p31 to p35 C50 ma p31 to p35 h level average output current v ohav C4 ma except p31 to p35 C40 ma p31 to p35 h level total maximum output current v ohtotalmax C50 ma except p31 to p35 C200 ma p31 to p35 h level total average output current v ohtotalav C20 ma except p31 to p35 C100 ma p31 to p35 power consumption p d 300 mw operating temperature t a C40 +85 c storage temperature tstg C55 +150 c
25 mb89940 series 2. recommended operating conditions (av cc = v cc = dv cc = 5.0 v, v ss = av ss = dv ss = 0.0 v) warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. 3. dc characteristics (av cc = v cc = dv cc = 5.0 v, v ss = av ss = dv ss = 0.0 v) (continued) parameter symbol value unit remarks min. typ. max. operating supply voltage range v cc av cc dv cc 3.5 5.5 v ram data retention supply voltage range v cc av cc dv cc 3.0 5.5 v operating temperature range t a C40 +85 c parameter symbol pin name condition value unit remarks min. typ. max. h level input voltage v ih p00 to p07, p10 to p17 p30 to p37, p40 to p47 0.7 v cc v cc + 0.3 v v ihs rst , mode, p20 to p27 0.8 v cc v cc + 0.3 v l level input voltage v il p00 to p07, p10 to p17 p30 to p37, p40 to p47 v ss - 0.3 0.3 v cc v v ils rst , mode, p20 to p27 v ss - 0.3 0.2 v cc v open-drain output pin application voltage v d v ss - 0.3 v cc + 0.3 v v d2 v ss - 0.3 v ss + 5.5 v mb89pv940/ 945 v d3 v ss - 0.3 v cc + 0.3 v mb89943 h level output voltage v oh p10 to p17, p20 to p27, p30, p36, p37 i oh = C2.0 ma 4.0 v v oh2 p31 to p36 i oh = C30 v cc = dv cc v cc - 0.5 v l level output voltage v ol p10 to p17, p20 to p27, p30, p36, p37, p40 to p44 i ol = 4.0 ma 0.4 v v ol2 p31 to p36 i ol = 30 ma v ss = dv ss 0.5v p40 p41 to p44 p41 to p44
26 mb89940 series (continued) (av cc = v cc = dv cc = 5.0 v, v ss = av ss = dv ss = 0.0 v) * : for information on t inst , see (4) instruction cycle in 4. ac characteristics. 4. ac characteristics (1) reset timing (av ss = v ss = dv ss , t a = C40 c to +85 c) t hcyl : one oscillation clock cycle time parameter symbol pin name condition value unit remarks min. typ. max. input leakage current i il1 mode, p10 to p17, p20 to p27, p30 to p37, p40 to p44 0.0 v< v i < v cc , v cc = dv cc C5 +5 m a without pull-up option pull-up resistance r pull rst , p12 to p17, p20 to p27 25 50 100 k w with pull-up option lcd internal bias voltage resister r lcd v0-v1, v1-v2, v2-v3 50 100 200 k w power supply current i cc v cc f c = 8 mhz, t inst * = 0.5 m s i cc = i(v cc ) + i(dv cc ) 12 20 ma mb89pv940 12 20 ma mb89943, MB89P945 i ccs f c = 8 mhz t inst * = 0.5 m s i ccs = i(v cc ) + i(dv cc ) in sleep mode 3 7ma i cch in stop mode t a = 25 c i cch = i(v cc ) + i(dv cc ) 510 m a i a av cc f c = 8 mhz i a = i(av cc ) a/d in operation 6 8ma i ah f c = 8 mhz i ah = i(av cc ) a/d stopped 510 m a input capacitance c in f = 1 mhz10pf external capacitor at vint c vint 0.1 m f mb89943 only parameter symbol condition value unit remarks min. max. rst l pulse width t zlzh 16 t hcyl ns
27 mb89940 series if power-on reset option is not activated, the external reset signal must be kept asserted until the oscillation is stabilized. (2) power-on profile (av ss = v ss = dv ss , t a = C40 c to +85 c) t hcyl : one oscillation clock cycle time note: power supply voltage should reach the minimum operation voltage within the specified default duration of the oscillation stabilization time. (3) clock timing (av ss = v ss = dv ss , t a = C40 c to +85 c) parameter symbol condition value unit remarks min. max. power supply voltage rising time t r 50ms mb89pv940, MB89P945 power supply voltage rising time t r 2 19 t hcyl ns mb89943 power-off minimum period t off 1ms parameter symbol condition value unit remarks min. max. clock frequency f c 18mhz clock cycle time t cyc 1000 125 ns input clock pulse width t wh t wl 20 ns input clock rising/falling time t cr t cf 10ns 0.2 v cc 0.8 v cc rst t zlzh 0.2 v 0.2 v 3.5 v 0.2 v t r v cc t off
28 mb89940 series (4) instruction cycle note: when operating at 8 mhz, the cycle varies with the set execution time. (5) peripheral input timing (av ss = v ss = dv ss , t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol value (typical) unit remarks instruction cycle (minimum execution time) t inst 4/f c , 8/f c , 16/f c , 64/f c m s (4/f c ) t inst = 0.5 m s when operating at f c = 8 mhz parameter symbol pin name value unit remarks min. max. peripheral input h pulse width t wh int0, int1, int2, ec 2 t inst * m s peripheral input l pulse width t wl int0, int1, int2, ec 2 t inst * m s 0.2 v cc x0 0.2 v cc x0 x1 t cyc when a crystal or ceramic resonator is used x0 x1 when an external clock is used open 0.2 v cc 0.8 v cc 0.8 v cc t cr t cf t wl t wl x0 and x1 timing and conditions clock conditions
29 mb89940 series 5. a/d converter electrical characteristics (av ss = v ss = dv ss , t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle in 4. ac characteristics. 6. a/d converter glossary ? resolution analog changes that are identifiable with the a/d converter when the number of bits is 8, analog voltage can be divided into 2 8 = 256. ? linearity error (unit: lsb) the deviation of the straight line connecting the zero transition point (0000 0000 ? 0000 0001) with the full-scale transition point (1111 1111 ? 1111 1110) from actual conversion characteristics ? differential linearity error (unit: lsb) the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value ? total error (unit: lsb) the difference between theoretical and actual conversion values parameter symbol pin name condition value unit remarks min. typ. max. resolution 8bit total error 1.5 lsb linearlity error 1.0 lsb differential linearlity error 0.9 lsb zero transition voltage v ot av ss C 1.0 lsb av ss + 0.5 lsb av ss + 2.0 lsb v mb89pv940/p945 av ss + 5/8 lsb av ss + 7/8 lsb av ss + 11/8 lsb v mb89943 full-scale transition voltage v fst av cc C 3.0 lsb av cc C 1.5 lsb av cc v mb89pv940/p945 av cc C 13/8 lsb av cc C 9/8 lsb av cc C 7/8 lsb v mb89943 interchannel disparity 0.5lsb a/d mode conversion time 44 t inst * m s mb89pv940/p945 52 t inst * m s mb89943 analog input current i ain 10 m a analog input voltage range 0av cc v int0, int1, int2, ec 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc t wl t wl
30 mb89940 series 7. notes on using a/d converter ? input impedance of the analog input pins the a/d converter used for the mb89940 series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after activating a/d conversion. for this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. therefore, it is recommended to keep the output impedance of the external circuit low (below 10 k w ). note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 m f for the analog input pin. ?error the smaller the | av cc C av ss |, the greater the error would become relatively. v ot v nt v (n + 1)t v fst digital output (1 lsb n + v ot ) 0000 0000 0000 0000 0001 0010 1111 1111 1110 1111 1 lsb = avr 256 linearity error = differential linearity error = analog input actual conversion value theoretical conversion value total error = v nt ?(1 lsb n + v ot ) 1 lsb v ( n + 1 ) t ?v nt 1 lsb ?1 1 lsb v nt ?(1 lsb n + 1 lsb) linearity error analog input equivalent circuit sample hold circuit analog channel selector close for 8 instruction cycles after activating a/d conversion. if the analog input impedance is higher than 10 k w , it is recommended to connect an external capacitor of approx. 0.1 m f. analog input pin comparator r = 6 k w . . c = 33 pf . .
31 mb89940 series 8. low supply voltage reset electrical characteristics 9. external voltage monitor interrupt electrical characteristics parameter symbol value unit remarks min. max. reset voltage v dl1 3.0 3.6 v when the voltage is dropping. refer to the register definition. v dl2 3.3 3.9 v v dl3 3.7 4.3 v hysteresis of reset voltage v hys 0.1 v when the voltage is recovering. delay time to reset t d 2.0 m s supply voltage slew rate dv/dt 0.1 v/ m s parameter symbol value unit remarks min. max. reference voltage v ref 1.18 1.38 v delay time to interrupt t d 2.0 m s refer to the register definition. input slew rate dv/dt 0.1 v/ m s
32 mb89940 series n instructions (136 instructions) execution instructions can be divided into the following four groups: ? transfer ? arithmetic operation ? branch ?others table 1 lists symbols used for notation of instructions. table 1 instruction symbols symbol meaning dir direct address (8 bits) off offset (8 bits) ext extended address (16 bits) #vct vector table number (3 bits) #d8 immediate data (8 bits) #d16 immediate data (16 bits) dir: b bit direct address (8:3 bits) rel branch relative address (8 bits) @ register indirect (example: @a, @ix, @ep) a accumulator a (whether its length is 8 or 16 bits is determined by the instruction in use.) ah upper 8 bits of accumulator a (8 bits) al lower 8 bits of accumulator a (8 bits) t temporary accumulator t (whether its length is 8 or 16 bits is determined by the instruction in use.) th upper 8 bits of temporary accumulator t (8 bits) tl lower 8 bits of temporary accumulator t (8 bits) ix index register ix (16 bits) ep extra pointer ep (16 bits) pc program counter pc (16 bits) sp stack pointer sp (16 bits) ps program status ps (16 bits) dr accumulator a or index register ix (16 bits) ccr condition code register ccr (8 bits) rp register bank pointer rp (5 bits) ri general-purpose register ri (8 bits, i = 0 to 7) indicates that the very is the immediate data. (whether its length is 8 or 16 bits is determined by the instruction in use.) ( ) indicates that the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.) (( )) the address indicated by the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.)
33 mb89940 series columns indicate the following: mnemonic: assembler notation of an instruction ~: the number of instructions #: the number of bytes operation: operation of an instruction tl, th, ah: a content change when each of the tl, th, and ah instructions is executed. symbols in the column indicate the following: ? C indicates no change. ? dh is the 8 upper bits of operation description data. ? al and ah must become the contents of al and ah prior to the instruction executed. ? 00 becomes 00. n, z, v, c: an instruction of which the corresponding flag will change. if + is written in this column, the relevant instruction will change its corresponding flag. op code: code of an instruction. if an instruction is more than one code, it is written according to the following rule: example: 48 to 4f ? this indicates 48, 49, ... 4f.
34 mb89940 series table 2 transfer instructions (48 instructions) notes: during byte transfer to a, t ? a is restricted to low bytes. operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (reverse arrangement of f 2 mc-8 family) mnemonic ~ # operation tl th ah n z v c op code mov dir,a mov @ix +off,a mov ext,a mov @ep,a mov ri,a mov a,#d8 mov a,dir mov a,@ix +off mov a,ext mov a,@a mov a,@ep mov a,ri mov dir,#d8 mov @ix +off,#d8 mov @ep,#d8 mov ri,#d8 movw dir,a movw @ix +off,a movw ext,a movw @ep,a movw ep,a movw a,#d16 movw a,dir movw a,@ix +off movw a,ext movw a,@a movw a,@ep movw a,ep movw ep,#d16 movw ix,a movw a,ix movw sp,a movw a,sp mov @a,t movw @a,t movw ix,#d16 movw a,ps movw ps,a movw sp,#d16 swap setb dir: b clrb dir: b xch a,t xchw a,t xchw a,ep xchw a,ix xchw a,sp movw a,pc 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ? (a) ( (ix) +off ) ? (a) (ext) ? (a) ( (ep) ) ? (a) (ri) ? (a) (a) ? d8 (a) ? (dir) (a) ? ( (ix) +off) (a) ? (ext) (a) ? ( (a) ) (a) ? ( (ep) ) (a) ? (ri) (dir) ? d8 ( (ix) +off ) ? d8 ( (ep) ) ? d8 (ri) ? d8 (dir) ? (ah),(dir + 1) ? (al) ( (ix) +off) ? (ah), ( (ix) +off + 1) ? (al) (ext) ? (ah), (ext + 1) ? (al) ( (ep) ) ? (ah),( (ep) + 1) ? (al) (ep) ? (a) (a) ? d16 (ah) ? (dir), (al) ? (dir + 1) (ah) ? ( (ix) +off), (al) ? ( (ix) +off + 1) (ah) ? (ext), (al) ? (ext + 1) (ah) ? ( (a) ), (al) ? ( (a) ) + 1) (ah) ? ( (ep) ), (al) ? ( (ep) + 1) (a) ? (ep) (ep) ? d16 (ix) ? (a) (a) ? (ix) (sp) ? (a) (a) ? (sp) ( (a) ) ? (t) ( (a) ) ? (th),( (a) + 1) ? (tl) (ix) ? d16 (a) ? (ps) (ps) ? (a) (sp) ? d16 (ah) ? (al) (dir): b ? 1 (dir): b ? 0 (al) ? (tl) (a) ? (t) (a) ? (ep) (a) ? (ix) (a) ? (sp) (a) ? (pc) C C C C C al al al al al al al C C C C C C C C C al al al al al al C C C C C C C C C C C C C C C al al C C C C C C C C C C C C C C C C C C C C C C C C C ah ah ah ah ah ah C C C C C C C C C C C C C C C C ah C C C C C C C C C C C C C C C C C C C C C C C C C dh dh dh dh dh dh dh C C dh C dh C C C dh C C al C C C dh dh dh dh dh C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 45 46 61 47 48 to 4f 04 05 06 60 92 07 08 to 0f 85 86 87 88 to 8f d5 d6 d4 d7 e3 e4 c5 c6 c4 93 c7 f3 e7 e2 f2 e1 f1 82 83 e6 70 71 e5 10 a8 to af a0 to a7 42 43 f7 f6 f5 f0
35 mb89940 series table 3 arithmetic operation instructions (62 instructions) (continued) mnemonic ~ # operation tl th ah n z v c op code addc a,ri addc a,#d8 addc a,dir addc a,@ix +off addc a,@ep addcw a addc a subc a,ri subc a,#d8 subc a,dir subc a,@ix +off subc a,@ep subcw a subc a inc ri incw ep incw ix incw a dec ri decw ep decw ix decw a mulu a divu a andw a orw a xorw a cmp a cmpw a rorc a rolc a cmp a,#d8 cmp a,dir cmp a,@ep cmp a,@ix +off cmp a,ri daa das xor a xor a,#d8 xor a,dir xor a,@ep xor a,@ix +off xor a,ri and a and a,#d8 and a,dir 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 (a) ? (a) + (ri) + c (a) ? (a) + d8 + c (a) ? (a) + (dir) + c (a) ? (a) + ( (ix) +off) + c (a) ? (a) + ( (ep) ) + c (a) ? (a) + (t) + c (al) ? (al) + (tl) + c (a) ? (a) - (ri) - c (a) ? (a) - d8 - c (a) ? (a) - (dir) - c (a) ? (a) - ( (ix) +off) - c (a) ? (a) - ( (ep) ) - c (a) ? (t) - (a) - c (al) ? (tl) - (al) - c (ri) ? (ri) + 1 (ep) ? (ep) + 1 (ix) ? (ix) + 1 (a) ? (a) + 1 (ri) ? (ri) - 1 (ep) ? (ep) - 1 (ix) ? (ix) - 1 (a) ? (a) - 1 (a) ? (al) (tl) (a) ? (t) / (al),mod ? (t) (a) ? (a) (t) (a) ? (a) (t) (a) ? (a) " (t) (tl) - (al) (t) - (a) (a) - d8 (a) - (dir) (a) - ( (ep) ) (a) - ( (ix) +off) (a) - (ri) decimal adjust for addition decimal adjust for subtraction (a) ? (al) " (tl) (a) ? (al) " d8 (a) ? (al) " (dir) (a) ? (al) " ( (ep) ) (a) ? (al) " ( (ix) +off) (a) ? (al) " (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) C C C C C C C C C C C C C C C C C C C C C C C dl C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 00 C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C dh C C C C dh C C C dh dh 00 dh dh dh C C C C C C C C C C C C C C C C C C C C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + C C C C C C C C C + + C C + + + C C C C C C C C C + + C C C C C C C C C C + + r C + + r C + + r C + + + + + + + + + + C + + + C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C 28 to 2f 24 25 26 27 23 22 38 to 3f 34 35 36 37 33 32 c8 to cf c3 c2 c0 d8 to df d3 d2 d0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1f 84 94 52 54 55 57 56 58 to 5f 62 64 65 a c ? ? ?? a c
36 mb89940 series (continued) table 4 branch instructions (17 instructions) table 5 other instructions (9 instructions) mnemonic ~ # operation tl th ah n z v c op code and a,@ep and a,@ix +off and a,ri or a or a,#d8 or a,dir or a,@ep or a,@ix +off or a,ri cmp dir,#d8 cmp @ep,#d8 cmp @ix +off,#d8 cmp ri,#d8 incw sp decw sp 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (dir) C d8 ( (ep) ) C d8 ( (ix) + off) C d8 (ri) C d8 (sp) ? (sp) + 1 (sp) ? (sp) C 1 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + + + + + + + + + + + + + + + C C C C C C C C 67 66 68 to 6f 72 74 75 77 76 78 to 7f 95 97 96 98 to 9f c1 d1 mnemonic ~ # operation tl th ah n z v c op code bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel blt rel bge rel bbc dir: b,rel bbs dir: b,rel jmp @a jmp ext callv #vct call ext xchw a,pc ret reti 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 if z = 1 then pc ? pc + rel if z = 0 then pc ? pc + rel if c = 1 then pc ? pc + rel if c = 0 then pc ? pc + rel if n = 1 then pc ? pc + rel if n = 0 then pc ? pc + rel if v " n = 1 then pc ? pc + rel if v " n = 0 then pc ? pc + rei if (dir: b) = 0 then pc ? pc + rel if (dir: b) = 1 then pc ? pc + rel (pc) ? (a) (pc) ? ext vector call subroutine call (pc) ? (a),(a) ? (pc) + 1 return from subrountine return form interrupt C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + C C C + C C C C C C C C C C C C C C C C C C C C C C C C C C restore fd fc f9 f8 fb fa ff fe b0 to b7 b8 to bf e0 21 e8 to ef 31 f4 20 30 mnemonic ~ # operation tl th ah n z v c op code pushw a popw a pushw ix popw ix nop clrc setc clri seti 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r C C C s C C C C C C C C 40 50 41 51 00 81 91 80 90
37 mb89940 series n instruction map 0123456789abcdef 0 nop swap ret reti pushw a popw a mov a,ext movw a,ps clri seti clrb dir: 0 bbc dir: 0,rel incw a decw a jmp @a movw a,pc 1 mulu a divu a jmp addr16 call addr16 pushw ix popw ix mov ext,a movw ps,a clrc setc clrb dir: 1 bbc dir: 1,rel incw sp decw sp movw sp,a movw a,sp 2 rolc a cmp a addc a subc a xch a, t xor a and a or a mov @a,t mov a,@a clrb dir: 2 bbc dir: 2,rel incw ix decw ix movw ix,a movw a,ix 3 rorc a cmpw a addcw a subcw a xchw a, t xorw a andw a orw a movw @a,t movw a,@a clrb dir: 3 bbc dir: 3,rel incw ep decw ep movw ep,a movw a,ep 4 mov a,#d8 cmp a,#d8 addc a,#d8 subc a,#d8 xor a,#d8 and a,#d8 or a,#d8 daa das clrb dir: 4 bbc dir: 4,rel movw a,ext movw ext,a movw a,#d16 xchw a,pc 5 mov a,dir cmp a,dir addc a,dir subc a,dir mov dir,a xor a,dir and a,dir or a,dir mov dir,#d8 cmp dir,#d8 clrb dir: 5 bbc dir: 5,rel movw a,dir movw dir,a movw sp,#d16 xchw a,sp 6 mov a,@ix +d cmp a,@ix +d addc a,@ix +d subc a,@ix +d mov @ix +d,a xor a,@ix +d and a,@ix +d or a,@ix +d mov @ix +d,#d8 cmp @ix +d,#d8 clrb dir: 6 bbc dir: 6,rel movw a,@ix +d movw @ix +d,a movw ix,#d16 xchw a,ix 7 mov a,@ep cmp a,@ep addc a,@ep subc a,@ep mov @ep,a xor a,@ep and a,@ep or a,@ep mov @ep,#d8 cmp @ep,#d8 clrb dir: 7 bbc dir: 7,rel movw a,@ep movw @ep,a movw ep,#d16 xchw a,ep 8 mov a,r0 cmp a,r0 addc a,r0 subc a,r0 mov r0,a xor a,r0 and a,r0 or a,r0 mov r0,#d8 cmp r0,#d8 setb dir: 0 bbs dir: 0,rel inc r0 dec r0 callv #0 bnc rel 9 mov a,r1 cmp a,r1 addc a,r1 subc a,r1 mov r1,a xor a,r1 and a,r1 or a,r1 mov r1,#d8 cmp r1,#d8 setb dir: 1 bbs dir: 1,rel inc r1 dec r1 callv #1 bc rel a mov a,r2 cmp a,r2 addc a,r2 subc a,r2 mov r2,a xor a,r2 and a,r2 or a,r2 mov r2,#d8 cmp r2,#d8 setb dir: 2 bbs dir: 2,rel inc r2 dec r2 callv #2 bp rel b mov a,r3 cmp a,r3 addc a,r3 subc a,r3 mov r3,a xor a,r3 and a,r3 or a,r3 mov r3,#d8 cmp r3,#d8 setb dir: 3 bbs dir: 3,rel inc r3 dec r3 callv #3 bn rel c mov a,r4 cmp a,r4 addc a,r4 subc a,r4 mov r4,a xor a,r4 and a,r4 or a,r4 mov r4,#d8 cmp r4,#d8 setb dir: 4 bbs dir: 4,rel inc r4 dec r4 callv #4 bnz rel d mov a,r5 cmp a,r5 addc a,r5 subc a,r5 mov r5,a xor a,r5 and a,r5 or a,r5 mov r5,#d8 cmp r5,#d8 setb dir: 5 bbs dir: 5,rel inc r5 dec r5 callv #5 bz rel e mov a,r6 cmp a,r6 addc a,r6 subc a,r6 mov r6,a xor a,r6 and a,r6 or a,r6 mov r6,#d8 cmp r6,#d8 setb dir: 6 bbs dir: 6,rel inc r6 dec r6 callv #6 bge rel f mov a,r7 cmp a,r7 addc a,r7 subc a,r7 mov r7,a xor a,r7 and a,r7 or a,r7 mov r7,#d8 cmp r7,#d8 setb dir: 7 bbs dir: 7,rel inc r7 dec r7 callv #7 blt rel l h
38 mb89940 series n mask options n ordering information no. part number mb89943 MB89P945 mb89pv940 specifying procedure specify when ordering masking set with eprom programmer setting not possible 1 pull-up resistors p12 to p17, p20 to p27 selectable per pin (p20 and p12 to p17 must be set to without pull-up resistor when they are used as lcd outputs.) can be set per pin fixed to without pull-up resistor 2 power-on reset with power-on reset without power-on reset fixed to with power-on reset setting possible fixed to with power-on reset 3 main clock oscillation stabilization time selection (when operating at 8 mhz) approx. 2 18 /f c (approx. 32.8 ms) approx. 2 17 /f c (approx. 16.4 ms) approx. 2 14 /f c (approx. 2.0 ms) selectable setting possible fixed to approx. 2 18 /f c (approx. 32.8 ms) 4 reset pin output with reset output without reset output fixed to with reset output setting possible fixed to with reset output part number package remarks mb89943pf MB89P945pf 48-pin plastic qfp (fpt-40p-m16) mb89pv940cf 48-pin ceramic mqfp (mqp-48c-p01)
39 mb89940 series n package dimension c 1994 fujitsu limited f48026s-1c-1 details of "a" part 17.20?.40 0.30?.06 (.012?002) 0.16(.006) m 13.60?.40 8.80 (.535?016) (.346) ref 0.15(.006) index details of "b" part 12 1 25 36 37 24 13 48 0.80(.0315)typ lead no. (.677?016) sq sq "a" 0.15(.006) 0.20(.008) 0.50(.020)max 0.15(.006)max 0~10 1.80?.30 (.071?012) "b" (stand off) 0.05(.002)min .472 ?004 +.012 ?.10 +0.30 12.00 .006 ?0004 +.002 ?.01 +0.05 0.15 2.70(.106)max (mounting height) dimensions in mm (inches) (fpt-48p-m16) 48-pin plastic qfp c 1994 fujitsu limited m48001sc-4-2 14.82?.35 (.583?014) 15.00?.25 (.591?010) 17.20(.677)typ pin no.1 index .430 ? +.005 ?.0 +0.13 10.92 1.02?.13 (.040?005) 7.14(.281) 8.71(.343) typ typ 0.30(.012)typ 4.50(.177)typ pad no.1 index 0.15?.05 (.006?002) 8.50(.335)max 0.60(.024)typ 1.10 +0.45 ?.25 +.018 ?010 .043 0.40?.08 (.016?003) 0.80?.22 (.0315?0087) 8.80(.346)ref 1.00(.040)typ 1.50(.059)typ pin no.1 index dimensions in mm (inches) (mqp-48c-p01) 48-pin ceramic mqfp
41 mb89940 series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9704 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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